Instruction set architecture: Difference between revisions
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Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "[[PowerPC]] CPU" uses some variant of the PowerPC ISA. Some CPUs, like the Intel [[Itanium]], can actually interpret instructions for more than one ISA; however this is often accomplished by software means rather than by designing the hardware to directly support both interfaces. (See [[emulator]]) | Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "[[PowerPC]] CPU" uses some variant of the PowerPC ISA. Some CPUs, like the Intel [[Itanium]], can actually interpret instructions for more than one ISA; however this is often accomplished by software means rather than by designing the hardware to directly support both interfaces. (See [[emulator]]) | ||
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[[Category:CZ Live]] | [[Category:CZ Live]] | ||
Revision as of 16:52, 30 March 2007
The instruction set architecture (ISA), is a part of computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), the native commands used by a particular CPU design.
Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. Some CPUs, like the Intel Itanium, can actually interpret instructions for more than one ISA; however this is often accomplished by software means rather than by designing the hardware to directly support both interfaces. (See emulator)